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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12524-3E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89890 Series
MB89898/899/P899/PV890
s OUTLINE
The MB89890 series is a line of single-chip microcontrollers containing a great variety of peripheral functions such as dual clock control systems, 4-stage operating speed controller, DTMF signal generator, timer, PWM timer, serial interface, modem, A/D converter and external interrupt, as well as compact instruction set.
s FEATURES
* * * * * * * * * * * * * * * F2MC-8L family CPU core Dual clock control system Maximum memory size: 64 Kbytes Minimum execution time: 0.5 s at 8 MHz Interrupt processing time: 4.5 s at 8 MHz I/O ports: max. 85 ports 21-bit time-base counter 8-bit PWM timer DTMF generator 8/16-bit timer 8-bit serial I/O Serial I/O with 1-byte buffer A/D converter Modem timer (pulse-width counter) Modem signal output
(Continued)
s PACKAGE
100-pin Plastic QFP 100-pin Ceramic MQFP
(FPT-100P-M06)
(MQP-100C-P01)
MB89890 Series
(Continued) * External interrupt: 16 channels * Power-on reset function * Low-power consumption modes (subclock mode, watch mode, sleep mode, stop mode) * CMOS technology
s PRODUCT LINEUP
Part number Item
MB89898
MB89899
MB89P899 One-time product OTPROM product 60 K x 8 bits (internal OTPROM) 2.0 K x 8 bits 8 bits 1 to 3 bytes 1, 8, 16 bits 136 Internal
MB89PV890 Piggyback/ evaluation product (for development) 60 K x 8 bits (external ROM)
Classification
Mass-produced products (mask ROM products) 48 K x 8 bits 60 K x 8 bits (internal mask ROM) (internal mask ROM) 1.5 K x 8 bits
ROM size RAM size Instruction bit length Instruction length Data bit length The number of instructions Clock generator Minimum execution time Interrupt processing time Ports ( ) indicate shared function ports. PWM timer Timer/counter Serial I/O A/D converter DTMF generator Soft modem receiving timer
0.5 s at 8 MHz to 8 s at 8 MHz, 61 s at 32.768 kHz 4.5 s at 8 MHz to 72 s at 8 MHz, 549.3 s at 32.768 kHz General-purpose output ports (N-ch open-drain): General-purpose output ports (CMOS): General-purpose I/O ports (N-ch open-drain): General-purpose I/O ports (CMOS): Total: 8 bits x 1 channel 8 bits x 2 channels or 16 bits x 1 channel 8-bit serial I/O (with 1-byte buffer) x 1 8 bits x 8 channels CCITT all-tone output capable (1 to 0(10), *, #, A to D) Single-tone output capable 5-bit noise reduction circuit + pulse-width measurement timer 21 (8) 8 (0) 8 (6) 48 (29) 85 (43)
(Continued)
2
MB89890 Series
(Continued)
Part number Item
MB89898
MB89899
MB89P899
MB89PV890
Soft modem transmitting circuit External interrupt Time-base timer Watch prescaler Standby mode Process Operating voltage* EPROM for use
approximately 1208 bps, approximately 2415 bps modem output 16 21 bits 15 bits Watch mode, subclock mode, sleep mode, stop mode CMOS 2.2 V to 6.0 V 2.7 V to 6.0 V MBM27C512-20TV
* : Varies with conditions such as operating frequencies.
s PACKAGE AND CORRESPONDING MODELS
Package FPT-100P-M06 MQP-100C-P01 : Available x x : Not available MB89898 MB89899 MB89P899 MB89PV890 x
Note: For more information about each package, see "s External Dimensions".
s DIFFERENCES AMONG MODELS
1. Memory Size
Before evaluating using the piggyback model, verify its difference from the model that will actually be used.
2. Current Consumption
* In the case of the MB89PV890, added is the current consumed by the EPROM which is connected to the top socket. * When operated at low speed the product with an OTPROM (EPROM) will consume more current than the product with a mask ROM. However, the same is current consumption in sleep/stop mode.
3. Mask Options
Functions that can be selected as options and how to designate these options vary with product. Before using options, check "s Mask Options". Take particular care on the following points: * Options are fixed on the MB89PV890. * Pull-up resistor options on the MB89P899 are in 2-bit units for P00 to P07, P10 to P17, P60 to P67, P90 to P97, and PA0 to PA7. Options are in 1-bit units for P40 to P44, P70 to P77, P80 to P87.
3
MB89890 Series
s PIN ASSIGNMENT
(Top view) PA7/INT3 PA6/INT2 PA5/INT1 PA4/INT0 PA3/INTB DTMF AVR (AVCC) VCC P57/AN07 P56/AN06 P55/AN05 P54/AN04 P53/AN03 P52/AN02 P51/AN01 P50/AN00 (AVSS) VSS PA2/INTA PA1/INT29 PA0/INT28 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VCC X1A X0A MOD0 MOD1 X0 X1 VSS RST P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P97/INT27 P96/INT26 P95/INT25 P94/INT24 P93/INT23 P92/INT22 P91/INT21 P90/INT20 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75/BSO2 P74/BSI2 P73/BSK2 VSS P72/SO2 P71/SI2 P70/SK2 P67/BSO1 P66/BSI1 P65/BSK1 P64 P63/MSKO
4
P25 P26 P27 P40 P41 P42 P43 P44 P30/PWM P31/BUZR P32/MSKI P33 P34 P35/SK1 P36/SI1 P37/SO1 P60/TMO1 P61/TMO2 P62/TCLK VCC (FPT-100P-M06)
MB89890 Series
(Top view) PA7/INT3 PA6/INT2 PA5/INT1 PA4/INT0 PA3/INTB DTMF AVR (AVCC) VCC P57/AN07 P56/AN06 P55/AN05 P54/AN04 P53/AN03 P52/AN02 P51/AN01 P50/AN00 (AVSS) VSS PA2/INTA PA1/INT29 PA0/INT28 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VCC X1A X0A MOD0 MOD1 X0 X1 VSS RST P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
O7 O8
CE
01 N.C. A0 A1 A2 A3 A4 A5 A6
N.C. A15 A13 A14 A12
A10
OE
N.C. A11 A9 A8
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P97/INT27 P96/INT26 P95/INT25 P94/INT24 P93/INT23 P92/INT22 P91/INT21 P90/INT20 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75/BSO2 P74/BSI2 P73/BSK2 VSS P72/SO2 P71/SI2 P70/SK2 P67/BSO1 P66/BSI1 P65/BSK1 P64 P63/MSKO
N.C.
VSS
O6
O5
O4
O3
VCC
132
* Pin assignment on package top (MB89PV890 only) Pin no. 101 102 103 104 105 106 107 108 Pin name N.C. A15 A12 A7 A6 A5 A4 A3 Pin no. 109 110 111 112 113 114 115 116 Pin name A2 A1 A0 N.C. O1 O2 O3 VSS Pin no. 117 118 119 120 121 122 123 124 Pin name N.C. O4 O5 O6 O7 O8 CE A10 Pin no. 125 126 127 128 129 130 131 132 Pin name OE N.C. A11 A9 A8 A13 A14 VCC
N.C.: Internally connected. Do not use. 5
P25 P26 P27 P40 P41 P42 P43 P44 P30/PWM P31/BUZR P32/MSKI P33 P34 P35/SK1 P36/SI1 P37/SO1 P60/TMO1 P61/TMO2 P62/TCLK VCC (MQP-100C-P01)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
101
A7
O2
MB89890 Series
s PIN DESCRIPTION
Pin no. QFP*1, MQP*2 6 7 3 2 4 5 9 10 to 17 18 to 25 26 to 33 39 40 41 42, 43 44, 45, 46 34 to 38 85 to 92 47, 48, 49 51 52 53, 54, 55 56, 57, 58 Pin name X0 X1 X0A X1A MOD0 MOD1 RST P00 to P07 P10 to P17 P20 to P27 P30/PWM P31/BUZR P32/MSKI P33, P34 P35/SK1, P36/SI1, P37/SO1 P40 to P44 P50/AN00 to P57/AN07 P60/TMO1, P61/TMO2, P62/TCLK P63/MSKO P64 P65/BSK1, P66/BSI1, P67/BSO1 P70/SK2, P71/SI2, P72/SO2 D E E G F F F F F C B Circuit type A Function Crystal oscillator pins (8 MHz) Crystal oscillator pins (32.768 kHz) Operation mode select pins Connect to VSS (GND) when using. Reset input pin General-purpose I/O ports General-purpose I/O ports General-purpose I/O ports General-purpose I/O port Also serves as an 8-bit PWM. General-purpose I/O port Also serves as a buzzer output. General-purpose I/O port Also serves as a modem timer. General-purpose I/O ports General-purpose I/O ports Also serve as an 8-bit serial I/O output 1. General-purpose I/O ports General-purpose output ports Also serve as an analog input. General-purpose I/O ports Also serve as an 8/16-bit timer. General-purpose I/O port Also serves as a modem output. General-purpose I/O port General-purpose I/O ports Also serve as a serial I/O output 1 with 1-byte buffer. General-purpose I/O ports Also serve as an 8-bit serial I/O output 2.
J H F
F F F
I
(Continued)
*1: FPT-100P-M06 *2: MQP-100C-P01
6
MB89890 Series
(Continued)
Pin no. QFP*1, MQP*2 60, 61, 62 63, 64 65 to 72 73 to 80 81, 82, 83 96, 97 to 100 95 1, 50 8, 59 93 84 94 Pin name P73/BSK2, P74/BSI2, P75/BSO2 P76, P77 P80 to P87 P90/INT20 to P97/INT27 PA0/INT28, PA1/INT29, PA2/INTA PA3/INTB, PA4/INT0 to PA7/INT3 DTMF VCC VSS VCC (AVCC) VSS (AVSS) AVR Circuit type I Function General-purpose I/O ports Also serve as a serial I/O output 2 with 1-byte buffer. General-purpose I/O ports General-purpose output ports General-purpose I/O ports External interrupt input is hysteresis input. General-purpose I/O ports External interrupt input is hysteresis input. General-purpose I/O ports External interrupt input is hysteresis input. DTMF signal output pin Power supply pin Power supply (GND) pin Power supply pin Power supply GND pin A/D converter reference input pin
I J F F
F
K - - - - -
*1: FPT-100P-M06 *2: MQP-100C-P01
7
MB89890 Series
s I/O CIRCUIT TYPE
Type Circuit Remarks
A
X1 N-ch X0 P-ch P-ch N-ch Main clock control signal
Main clock * Oscillator feedback resistor: approximately 2 M at 5 V
B
X1A N-ch X0A P-ch P-ch N-ch Subclock control signal
Subclock * Oscillator feedback resistor: approximately 4.5 M at 5 V
C
D
R P-ch
* Output pull-up resistor (P-ch) At approximately 50 k/5 V * Hysteresis input
N-ch
E
R P-ch
* CMOS output * CMOS input * Pull-up resistor optional
P-ch
N-ch
(Continued)
8
MB89890 Series
(Continued)
Type Circuit Remarks
F
R P-ch
* CMOS output * Hysteresis input * Pull-up resistor optional
P-ch
N-ch
G
P-ch
* CMOS output
N-ch
H
P-ch
* N-ch open-drain output * Analog input
N-ch Analog input
I
R P-ch
* N-ch open-drain output * Hysteresis input * Pull-up resistor optional
N-ch
(Continued)
9
MB89890 Series
(Continued)
Type Circuit Remarks
J
R P-ch
* N-ch open-drain output * Pull-up resistor optional
N-ch
K
* DTMF analog output
OPAMP
10
MB89890 Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in "s Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although operation is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required for even power-on reset (optional) and release from stop mode.
11
MB89890 Series
s PROGRAMMING TO THE EPROM ON THE MB89P899
The MB89P899 is a one-time PROM version of the MB89890 series.
1. Features
* 60-Kbyte PROM on chip * Option can be set using the EPROM programmer. * Equivalency to the MBM27C1001, in EPROM mode (when programmed with the EPROM programmer), supports 4-byte programming mode.
2. Memory Space
Memory space in each mode such as 60-Kbyte PROM, option area is diagrammed below.
Address Single chip EPROM mode (Corresponding addresses on the EPROM programmer) 00000H I/O 00080H RAM 2 KB 00880H Not available 00FE4H Option area 00FFCH 01000H PROM 60 KB 0FFFFH 0FFFFH 00FFCH 01000H PROM 60 KB 00FE4H Option area Not available
00000H
Not available
1FFFFH
3. Programming to the EPROM
In EPROM mode the MB89P899 functions equivalent to the MBM27C1001. This allows the EPROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. When the operating ROM area for a single chip is 60 Kbytes (01000H to 0FFFFH ) the EPROM can be programmed as follows: * Programming procedure (1) Set the EPROM programmer to MBM27C1001. (2) Load program data into the EPROM programmer at 01000H to 0FFFFH. Load option data into addresses 00FE4H to 00FFCH. (For information about each corresponding options, see "7. Setting OTPROM Options.") (3) Program to 00FE4H to 00FFCH, and 01000H to 0FFFFH with the EPROM programmer. 12
MB89890 Series
4. Recommended Screening Conditions
High-Temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program.
Program, verify
Aging +150C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
Due to its nature, bit programming test can't be conducted as Fujitsu delivery test. For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Part number MB89P899 Package QFP-100 Compatible socket adapter Sun Hayato Co., Ltd. ROM-100QF-32DP-8LA
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106
13
MB89890 Series
7. Setting OTPROM Options
The programming procedure is the same as that for the program data. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map. * PROM Option Bitmap
Address
Bit 7 Vacancy
Bit 6 Vacancy
Readable and writable
Bit 5 Vacancy
Readable and writable
Bit 4
Single/ double clock 1: 2 clock sytems 0: 1 clcok system
Bit 3 Reset output 1: Yes 0: No P07, P06 Pull-up 1: No 0: Yes P37, P36 Pull-up 1: No 0: Yes P97, P96 Pull-up 1: No 0: Yes P43 Pull-up 1: No 0: Yes P73 Pull-up 1: No 0: Yes P83 Pull-up 1: No 0: Yes
Bit 2 Power-on reset 1: Yes 0: No P05, P04 Pull-up 1: No 0: Yes P35, P34 Pull-up 1: No 0: Yes P95, P94 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes P72 Pull-up 1: No 0: Yes P82 Pull-up 1: No 0: Yes
Bit 1
Bit 0
00FE4H Readable
and writable
Oscillation stabilization time 11 218/FCH 10 216/FCH 01 212/FCH 00 23/FCH P03, P02 Pull-up 1: No 0: Yes P33, P32 Pull-up 1: No 0: Yes P93, P92 Pull-up 1: No 0: Yes P41 Pull-up 1: No 0: Yes P71 Pull-up 1: No 0: Yes P81 Pull-up 1: No 0: Yes P01, P00 Pull-up 1: No 0: Yes P31, P30 Pull-up 1: No 0: Yes P91, P90 Pull-up 1: No 0: Yes P40 Pull-up 1: No 0: Yes P70 Pull-up 1: No 0: Yes P80 Pull-up 1: No 0: Yes
P17, P16 Pull-up 00FE8H 1: No 1: Yes P67, P66 Pull-up 00FECH 1: No 0: Yes PA7, PA6 Pull-up 00FF0H 1: No 0: Yes Vacancy
P15, P14 Pull-up 1: No 1: Yes P65, P64 Pull-up 1: No 0: Yes PA5, PA4 Pull-up 1: No 0: Yes Vacancy
P13, P12 Pull-up 1: No 0: Yes P63, P62 Pull-up 1: No 0: Yes PA3, PA2 Pull-up 1: No 0: Yes Vacancy
P11, P10 Pull-up 1: No 0: Yes P61, P60 Pull-up 1: No 0: Yes PA1, PA0 Pull-up 1: No 0: Yes
P44 Pull-up 00FF4H Readable Readable Readable 1: No and writable and writable and writable 0: Yes P77 Pull-up 00FF8H 1: No 0: Yes P87 Pull-up 00FFCH 1: No 0: Yes P76 Pull-up 1: No 0: Yes P86 Pull-up 1: No 0: Yes P75 Pull-up 1: No 0: Yes P85 Pull-up 1: No 0: Yes P74 Pull-up 1: No 0: Yes P84 Pull-up 1: No 0: Yes
Notes: * Note that option area address values are equivalent to every fourth address to accommodate 4-byte programming mode. * Each bit is set to `1' as the initialized value, therefore the pull-up option is not selected.
14
MB89890 Series
s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 (Rectangle) Adapter socket part mumber ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106
3. Memory Space
MB89PV890 0000H I/O 0080H MBM27C512-20TV
0100H Register 0200H RAM 2 KB 0880H 1000H External ROM 60 KB FFFFH FFFFH 1000H EPROM 60 KB
4. Programming Procedure
(1) Set the EPROM programmer to MBM27C512-20TV. (2) Load program data into the EPROM programmer at 1000H to FFFFH. (3) Program to 1000H to FFFFH with the EPROM programmer.
15
MB89890 Series
s BLOCK DIAGRAM
CMOS I/O port 3 Timebase timer 8-bit PWM timer RST Reset circuit (watchdog) Buzzer output Modem timer P30/PWM
P31/BUZR P32/MSKI P33 P34 P35/SK1 P36/SI1 P37/SO1 5
X0 X1
Oscillator (max. 8 MHz)
Clock control
8-bit serial I/O
X0A X1A 8 P0 0 to P07
Oscillator (32.768 kHz)
N-ch open-drain output port 4 N-ch open-drain output port 5 8-bit A/D converter 8 8
P40 to P44
CMOS I/O port 0
8 P1 0 to P17 CMOS I/O port 1 Internal bus Internal bus
P50/AN00 to P57/AN07
CMOS I/O port 6 8/16-bit timer P60/TMO1 P61/TMO2 P62/TCLK P63/MSKO P64 P65/BSK1 P66/BSI1 P67/BSO1
P2 0 to P27
8 CMOS output port 2
Modem output
8-bit serial I/O with 1-byte buffer RAM 1.5 Kbytes or 2.0 Kbytes
F 2 M C- 8L CPU
ROM 48 Kbytes or 60 Kbytes
N-ch open-drain I/O port 7 8 N-ch open-drain output port 8
P70/SK2 P71/SI2 P72/SO2 P73/BSK2 P74/BSI2 P75/BSO2 P76 P77
P80 to P87 8
DTMF
DTMF generator
CMOS I/O pots 9, A 4 12
The other pins VCC x 2, V SS x 2 M O D0, M O D1 AVCC, AVR, AV SS
External interrupt 2
4
External interrupt 1
4
P90/INT20 to P97/INT27 PA0/INT28 to PA3/INTB PA4/INT0 to PA7/INT3
16
MB89890 Series
s CPU CORE
1. Memory Space
The microcontrollers of the MB89890 series offer 64 Kbytes of memory for storing all of I/O, data, and program areas. The I/O area is allocated from the lowest address. The data area is allocated immediately above the I/ O area. The data area can be divided into register, stack, and direct areas, according to the application. The program area is allocated from exactly the opposite end, that is, near the highest address. The tables of interrupt reset vectors and vector call instructions are allocated from the highest address within the program area. The memory space of the MB89890 series is structured as illustrated below: * Memory Space
MB89898 0000H I/O 007FH 0080H 007FH 0080H 0000H I/O 007FH 0080H MB89899 0000H I/O 007FH 0080H MB89P899 0000H I/O MB89PV890
00FFH 0100H Register 01FFH 0200H 067FH 0680H
00FFH 0100H Register 01FFH 0200H
00FFH 0100H Register 01FFH 0200H
00FFH 0100H Register 01FFH 0200H
RAM 1.5 KB
RAM 2.0 KB
RAM 2.0 KB
RAM 2.0 KB
087FH 0880H
087FH 0880H
087FH 0880H
0FFFH 1000H 3FFFH 4000H ROM 48 KB ROM 60 KB
0FFFH 1000H ROM 60 KB
0FFFH 1000H External ROM 60 KB
FFFFH
FFFFH
FFFFH
FFFFH
17
MB89890 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated hardware registers in the CPU and general-purpose memory registers. The following dedicated registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP) : Stack pointer (SP) : Program status (PS) : A 16-bit-long register for indicating the instruction storage positions A 16-bit-long temporary register for arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit-long register which is used for arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit-long register for index modification A 16-bit-long pointer for indicating a memory address A 16-bit-long pointer for indicating a stack area A 16-bit-long register for storing a register pointer, a condition code
Initial value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH indeterminate indeterminate indeterminate indeterminate indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are indeterminate.
16 bits PC A T IX EP SP PS
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR) (see the diagram below). * Structure of the Program Status Register
15 PS
14
13 RP
12
11
10
9
8
7 H
6 I
5
4
3 N
2 Z
1 V
0 C
Vacancy Vacancy Vacancy
IL1, 0
RP
CCR
18
MB89890 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. * Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes b1 b0
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and bits for control of CPU operations at the time of an interrupt. H-flag: Set to `1' when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to `0' otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is enabled when this flag is set to `1'. Interrupt is disabled when the flag is cleared to `0'. Cleared to `0' at the reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 0 1 2 3 Low High-low High
N-flag: Set to `1' if the highest bit becomes `1' as the result of an arithmetic operation. Cleared to `0' otherwise. Z-flag: V-flag: Set to `1' when an arithmetic operation results in `0'. Cleared to `0' otherwise. Set to `1' if the complement on `2' overflows as a result of an arithmetic operation. Cleared to `0' if the overflow does not occur.
C-flag: Set to `1' when a carry or borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to `0' otherwise. Set to the shift-out value in the case of a shift instruction.
19
MB89890 Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit-long register for storing data The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used. The bank currently in use is indicated by the register bank pointer (RP). * Register Bank Configuraiton
This address = 0100H + 2 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area
20
MB89890 Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) PDR9 DDR9 PDRA DDRA SMR SDR CNTR COMR (R/W) PDR8 (R/W) (R/W) (R/W) PDR6 DDR6 PDR7 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) SCC SMC WDTC TBTC WPCR PDR3 DDR3 PDR4 BZCR PDR5 Write/read (R/W) (W) (R/W) (W) (R/W) Register name PDR0 DDR0 PDR1 DDR1 PDR2 Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register Vacancy Vacancy System clock control register Standby control register Watchdog control register Time-base timer control register Watch prescaler control register Port 3 data register Port 3 data direction register Port 4 data register Buzzer register Port 5 data register Vacancy Port 6 data register Port 6 direction register Port 7 data register Vacancy Port 8 data register Vacancy Port 9 data register Port 9 data direction register Port A data register Port A data direction register Serial mode register Serial data register PWM control register PWM compare register
(Continued)
21
MB89890 Series
(Continued)
Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH (R/W) SSEL (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ADC1 ADC2 ADCD EIE1 EIF1 EIE2 EIF2 MDC1 MDC2 MLDH MLDL Write/read (R/W) (R/W) (R/W) (R/W) (W) (R) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Register name DTMC DTMD SBMR SBFR SBUFW SBUFR SBDR T2CR T1CR T2DR T1DR MODC MODA Register description DTMF control register DTMF data register Serial mode register with1-byte buffer Serial flag register with1-byte buffer Serial write register with1-byte buffer Serial read register with1-byte buffer Serial data register with1-byte buffer Timer 2 control register Timer 1 control register Timer 2 data register Timer 1 data register Modem output control register Modem output data register Vacancy A/D converter control register 1 A/D converter control register 2 A/D converter data register External interrupt 1 enable register External interrupt 1 flag register External interrupt 2 enable register External interrupt 2 flag register Modem timer control 1 register Modem timer control 2 register Modem timer "H" level data register Modem timer "L" level data register Vacancy Vacancy Vacancy Vacancy Vacancy Serial I/O port switching register Vacancy Vacancy
(Continued)
22
MB89890 Series
(Continued)
Address 40H to 7BH 7CH 7DH 7EH 7FH Note: Do not use vacancies. (W) (W) (W) ILR1 ILR2 ILR3 Write/read Register name Vacancy Interrupt level register 1 Interrupt level register 2 Interrupt level register 3 Vacancy Register description
23
MB89890 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol VCC
Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Max. VSS + 7.0 VSS + 7.0 VSS + 7.0 VCC + 0.3 VSS + 7.0 VCC + 0.3 20 10 120 40 -20 -10 -60 -20 200 +85 +150
Unit V V V V V V mA mA mA mA mA mA mA mA mW C C Peak value
Remarks
Power supply voltage
AVCC AVR
Set VCC = AVCC* AVR must not exceed "AVCC + 0.3 V". Except P40 to P44, P70 to P77, P80 to P87 P40 to P44, P70 to P77, P80 to P87
Input voltage
VI VSS - 0.3
Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg
VSS - 0.3 -20 -55
Specified by the average value of 1 hour. Peak value Specified by the average value of 1 hour. Peak value Specified by the average value of 1 hour. Peak value Specified by the average value of 1 hour.
* : Use AVCC and VCC set to the same voltage. Take care so that AVCC does not exceed VCC, such as when power is turned on. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
24
MB89890 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Symbol VCC AVCC AVR
Value Min. 2.2* 1.5 2.0 -20 Max. 6.0 6.0 AVCC +85
Unit V V V C
Remarks See Figure 1. Retains the RAM state in the stop mode
Power supply voltage
Operating temperature
TA
* : This value varies with the DTMF generator assurance range.
Figure 1 Operation Assurance Range 6 : Highest gear speed : Lowest gear speed
5 Operating voltage (V)
Operation assurance range
4
3
2
1
1
2
3
4
5
6
7
8
9
10
Main clock operating frequency (MHz)
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 25
MB89890 Series
3. DC Characteristics
(AVCC = VCC = 5.0 V10%, AVSS = VSS = 0.0 V, TA = -20C to +85C)
Parameter
Symbol
Pin
P00 to P07, P10 to P17 P30 to P37, P60 to P67, P90 to P97, PA0 to PA7, RST, MOD0, MOD1, X0, X0A P00 to P07, P10 to P17 P30 to P37, P60 to P67, P90 to P97, PA0 to PA7, RST, MOD0, MOD1, X0, X0A P40 to P47, P70 to P77, P80 to P87 P50 to P57 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67, P90 to P97, PA0 to PA7 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67, P90 to P97, PA0 to PA7 RST P40 to P44, P70 to P77, P80 to P87 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P44, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA7, MOD0, MOD1
Condition -- -- -- --
Value Min. 0.7 VCC 0.8 VCC
VSS - 0.3 VSS - 0.3
Typ. -- -- -- --
Max.
VCC + 0.3
Unit V V V V
Remarks
VIH "H" level input voltage VIHS VIL "L" level input voltage VILS
VCC + 0.3
0.3 VCC
0.2 VCC
Open-drain output pin VD applied voltage
-- --
VSS - 0.3 VSS - 0.3
-- --
VSS + 7.0 VCC + 0.3
V V
N-ch opendrain N-ch opendrain
"H" level output VOH voltage
IOH = -2.0 mA
2.4
--
--
V
VOL1 "L" level output voltage VOL2 VOL3
IOL = 4.0 mA IOL = 4.0 mA IOL = 8.0 mA
-- -- --
-- -- --
0.4 0.4 0.6
V V V
Input leakage current (Hi-z output leakage current)
ILI
0.45 V < VI < VCC
--
--
5
A
(Continued)
26
MB89890 Series
(Continued)
(AVCC = VCC = 5.0 V10%, AVSS = VSS = 0.0 V, TA = -20C to +85C)
Parameter
Symbol
Pin
Condition
FCH = 4 MHz VCC = 5.0 V in the main clock operation FCH = 4 MHz VCC = 3.0 V in the main clock operation FCH = 8 MHz VCC = 5.0 V in the main clock operation FCH = 8 MHz VCC = 3.0 V in the main clock operation FCH = 4 MHz VCC = 5.0 V in the main sleep mode FCH = 8 MHz VCC = 5.0 V in the main sleep mode FCL = 32.768 kHz VCC = 3.0 V in the subclock sleep mode TA = +25C VCC = 3.0 V in the subclock stop mode
Value Min. Typ. Max.
Unit
Remarks
--
6
9
mA
Highest gear speed
--
1.2
1.8
mA
Lowest gear speed
ICC
--
13
26
mA
When DTMF operation is stopped
Highest gear speed
--
3
5
mA
Lowest gear speed
Power supply current
VCC
--
2.5
4
mA
Highest gear speed
ICCS1
--
4
8
mA
Highest gear speed
ICCS2
--
15
2.5
A
ICCH1
--
--
1
A
(Continued)
27
MB89890 Series
(Continued)
(AVCC = VCC = 5.0 V10%, AVSS = VSS = 0.0 V, TA = -20C to +85C)
Parameter
Symbol
Pin
Condition
TA = +85C VCC = 3.0 V in the subclock stop mode FCL = 32.768 kHz VCC = 3.0 V in the subclock operation FCL = 32.768 kHz VCC = 3.0 V in the watch mode FCH = 4 MHz VCC = 5.0 V in the main clock operation
Value Min. Typ. Max.
Unit
Remarks
ICCH2
When DTMF operation is stopped
--
1
10
A
ICSB
--
50
75
A
ICCT
--
--
15
A
VCC
--
8
12
mA
Highest gear speed
During DTMF operation
Power supply current
ICCD
FCH = 4 MHz VCC = 3.0 V in the main clock operation FCH = 8 MHz VCC = 5.0 V in the main clock operation FCH = 8 MHz VCC = 3.0 V in the main clock operation
--
2.3
3.4
mA
Lowest gear speed
--
17
31
mA
Highest gear speed
--
6
11
mA
Lowest gear speed
IA AVCC IAH Other than AVCC, AVSS, VCC, and VSS FCH = 8 MHz
--
1.5
3.5
When A/D mA conversion is operating When A/D conversion A is not operating pF
--
1
5
Input capacitance CIN
--
--
10
--
28
MB89890 Series
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V10%, VSS = 0.0 V, TA = -20C to +85C)
Parameter RST "L" pulse width RST "H" pulse width
Symbol tZLZH tZHZL
Condition --
Value Min. 48 tXCYL 24 tXCYL Max. -- --
Unit ns ns
Remarks
Note: tXCYL is the oscillation cycle input to the X0.
tZLZH RST 0.2 VCC
tZHZL 0.8 VCC 0.2 VCC 0.2 VCC
(2) Power-on Reset
(VSS = 0.0 V, TA = -20C to +85C)
Parameter Power supply rising time Power supply cut-off time
Symbol tR tOFF
Condition --
Value Min. -- 1 Max. 50 --
Unit ms ms
Remarks Power-on reset function only Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time selected. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR 2.0 V
tOFF
VCC
0.2 V
0.2 V
0.2 V
29
MB89890 Series
(3) Clock Timing
(VCC = +5.0 V10%, VSS = 0.0 V, TA = -20C to +85C)
Parameter Clock frequency Clock cycle time
Symbol FCH FCL tHCYL tLCYL PWH PWL PWLH PWLL tCR1 tCF1 tCR2 tCF2
Pin name X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0 X0A
Condition
Value Min. 1 -- 125 -- Typ. -- 32.768 -- 30.5 -- 15.2 -- -- Max. 8 -- 1000 -- -- -- 24 200
Unit
Remarks
MHz Main clock kHz ns s ns s ns External clock ns Subclock Main clock Subclock External clock External clock
Input clock pulse width
--
20 -- -- --
Input clock rising/falling time
30
MB89890 Series
* X0 and X1 Timing and Conditions of Applied Voltage
tHCYL 0.8 VCC X0 0.2 VCC PWH PWL tCF1 tCR1
* Main Clock Conditions
When a crystal or ceramic resonator is used
When an external clock is used
X0
X1
X0
X1 Open
FCH C0 C1 FCH
* X0A and X1A Timing and Conditions of Applied Voltage
tLCYL 0.8 VCC X0A 0.2 VCC PWHL PWLL tCF2 tCR2
* Subclock Conditions
When a crystal or ceramic resonator is used
When an external clock is used
X0A
X1A Rd FCL
X0A
X1A Open FCL
C0
C1
31
MB89890 Series
(4) Instruction Cycle Parameter Symbol Value 4/FCH, 8/FCH, 16/FCH, 64/FCH 2/FCL Unit s s Remarks (4/FCH) tinst = 0.5 s when operating at FCH = 8 MHz tinst = 61.036 s when operating at FCL = 32.768 kHz
Instruction cycle tinst (minimum execution time)
*1: When operating at the main clock, tinst varies with the execution time (gear) setting, within the following range: Min. = 4/FCH, Max. = 64/FCH. *2: When operating at the subclock, tinst = 2/FCL. (5) Recommended Resonator Manufacturers * Sample Application of Piezoelectric Resonator (FAR Series)
X0
X1 FAR*1
C1*2
C2*2 *1: Fujitsu Acoustic Resonator
FAR part number Frequency (MHz) (built-in capacitor type) FAR-C4 A-03580- 01 FAR-C4 G-10000- 05 Inquiry: FUJITSU LIMITED 3.58 10.00
Initial deviation of FAR frequency (TA = +25C) 0.5% 0.5%
Temperature Loading characteristics of FAR frequency capacitors*2 (TA = -20C to +60C) 0.5% Built-in 0.5%
32
MB89890 Series
* Sample Application of Ceramic Resonator
X0
X1
C1
C2
* Mask ROM products Resonator manufacturer Murata Mfg. Co., Ltd. Resonator CSA8.00MTZ CST8.00MTW Frequency (MHz) 8.00 C1 (pF) 30 Built-in C2 (pF) 30 Built-in R Not required Not required
Inquiry: Murata Mfg. Co., Ltd * Murata Electronics North America. Inc.: TEL 1-404-436-1300 * Murata Europe Mnagement GmbH: TEL 49-911-66870 * Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233
33
MB89890 Series
(6) Serial I/O Timing
(VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -20C to +85C)
Parameter Serial clock cycle time SCK SO time Valid SI SCK SCK valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO time Valid SI SCK SCK valid SI hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
Pin name SCK SCK, SO SI, SCK SCK, SI SCK SCK, SO SI, SCK SCK, SI
Condition
Value Min. 2 tinst* -200 200 200 1 tinst* 1 tinst* Max. -- 200 -- -- -- -- 200 -- --
Unit s ns ns ns s s ns ns ns
Remarks
Internal shift clock mode
External shift clock mode
0 200 200
2 x tXCYL 2 x tXCYL
* : For information on tinst, see "(4) Instruction Cycle." * Internal Shift Clock Mode
tSCYC SCK 2.4 V 0.8 V tSLOV 2.4 V 0.8 V tIVSH SI 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.8 V
SO
* External Shift Clock Mode
tSLSH SCK 0.8 VCC 0.2 VCC 0.2 VCC tSLOV SO 2.4 V 0.8 V tIVSH SI 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC tSHSL 0.8 VCC
34
MB89890 Series
(7) Peripheral Input Timing
(VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -20C to +85C)
Parameter Peripheral input "H" level pulse width Peripheral input "L" level pulse width
Symbol tILIH tIHIL
Pin INT20 to INTA INT0 to INT3 INT20 to INTA INT0 to INT3
Value Min. 2 tinst* 2 tinst* Max. -- --
Unit s s
Remarks
* : For information on tinst, see "(4) Instruction Cycle."
tIHIL INT20 to INTA INT0 to INT3 0.2 VCC 0.8 VCC 0.2 VCC
tILIH 0.8 VCC
35
MB89890 Series
(8) Electrical Characteristics of DTMF Generator
(AVSS = VSS = 0.0 V, TA = -20C to +85C)
Parameter Operating voltage range
Symbol --
Condition -- VCC = 2.5 V to 6.0 V
Value Min. 2.5 Typ. 5.0 Max. 6.0
Unit V
Remarks
Output load requirements
RO
20
--
--
k
Defined when the DTMF pin is connected to a pull-down resistor.
DTMF output offset voltage (at signal output) DTMF output amplitude (ROW single tone) Difference between COLUMN and ROW levels Distortion ratio
VMOF VMFOR RMF --
VCC = 5.0 V VCC = 5.0 V -- --
-- -16.3 1.6 --
0.4 -14.0 2.0 --
-- -12.5 2.4 7
V dBm dB % When the DTMF pin is open. RO = 200 k
* Output Level Measurement Circuit
VCC X0 0.1 F 8 MHz X1 VSS DTMF RO -48 dB/oct Lowpass filter 16.0 kHz Audio analizer Output level
36
MB89890 Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -20C to +85C)
Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Interchannel disparity A/D mode conversion time Sense mode conversion time Analog port input current Analog input voltage Reference voltage
Symbol
Pin name
Condition
Value Min. -- -- Typ. -- -- -- --
AVSS + 0.5 LSB AVR - 1.5 LSB
Max. 8 1.5 1.0 0.9
AVSS + 1.5 LSB AVR + 1.5 LSB
Unit bit LSB LSB LSB mV mV LSB s s A V V A
Remarks
-- AVR = AVCC = 5.0 V V0T -- VFST
-- --
AVSS - 1.5 LSB AVR - 1.5 LSB
1 LSB = AVR/256
-- -- -- -- -- IAIN -- -- IR AN0 to AN7 -- 0.0 0.0 -- AVR IRH AVR = AVCC = 5.0 V --
-- 44 tinst* 12 tinst* -- -- -- 100
0.5 -- -- 10 AVR AVCC 300
Reference voltage supply current
When starting A/D conversion When starting A/D conversion
--
1
A
* : For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics."
6. A/D Converter Glossary
* Resolution Analog changes that are identifiable by the A/D converter When the number of bits is 8, analog voltage can be divided into 28 = 256. * Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point ("0000 0000" "0000 0001") with the full-scale transition point ("1111 1111" "1111 1110") from actual conversion characteristics * Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value * Total error (unit: LSB) The difference between theoretical and actual conversion values
37
MB89890 Series
Digital output 1111 1111 1111 * 1110
* * * * * * * * * * * * * * * * * * *
Theoretical conversion value Actual conversion value (1 LSB x N + VOT) AVR 256 VNT - (1 LSB x N + VOT) 1 LSB V( N + 1 ) T - VNT - 1 1 LSB VNT - (1 LSB x N + 1 LSB) 1 LSB
1 LSB =
Linearity error = Differential linearity error = Total error = 0010 0001 0000 VOT VNT V(N + 1)T VFST Analog input
Linearity error
0000 0000 0000
7. Notes on Using A/D Converter
* Input impedance of the analog input pins The A/D converter used for the MB89890 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after starting A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of approx. 0.1 F for the analog input pin. Analog Input Equivalent Circuit
Analog input pin Comparator If the analog input impedance is higher than 10 k, it is recommended to connect an external capacitor of approx. 0.1 F. . R = 6 k . Close for 8 instruction cycles after starting A/D conversion. Analog channel selector Sample hold circuit . C = 33 pF .
* Error The smaller the | AVR - AVSS |, the greater the error would become relatively. * Order of turning on A/D converter and analog input Make sure to turn on the digital power supply (VCC) before or at the same time with turning on the A/D converter power supply (AVCC, AVSS) and application of AN00 to AN07. To turn off the power, turn off the A/D converter power supply (AVCC, AVSS) and stop the analog input (AN00 to AN07) before or at the same time with turning off the digital power supply (VCC). 38
MB89890 Series
s ELECTRICAL CHARACTERISTICS
(1) "L" Level Output Voltage
VOL vs. IOL
V OL (V) 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 1 2 V CC = 2.2 V V CC = 2.5 V V CC = 3.0 V V CC = 4.0 V V CC = 5.0 V V CC = 6.0 V V CC - V OH (V) V CC = 2.2 V 1.1 T A = +25C 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 -.5 -1.0 -1.5 -2.0 V CC = 2.5 V
(2) "H" Level Output Voltage
V CC - VOH vs. IOL
V CC = 3.0 V V CC = 4.0 V V CC = 5.0 V V CC = 6.0 V
T A = +25C 3 4 5 6 7 8 9 10 I OL (mA)
-2.5 -3.0 I OH (mA)
(3) "H" Level Input Voltage/"L" Level Input Voltage (4) "H" Level Input Voltage/"L" Level Input Voltage (CMOS Input) (Hysteresis Input)
V IN vs. V CC V IN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1.00 2.00 3.00 4.00 5.00 6.00 7.00 V CC (V) -0 .00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 V CC (V) V ILS V IN vs. V CC T A = +25C V IHS
V IN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 -0 .00 T A = +25C
V IHS : "H" level input voltage threshold as hysteresis input V ILS : "L" level input voltage threshold as hysteresis input
39
MB89890 Series
(5) Power Supply Current (External Clock)
Characteristics of Current Consumption in the Main Clock Operation I CC (mA) I CC vs. V CC 10 9 T A = +25C F CH = 8 MHz 8 7 6 5 4 3 2 1 0 2 3 4 5 6 V CC (V)
Characteristics of Current Consumption in the DTMF and Main Clock Operation I CCD vs. V CC I CCD (mA) 12 11 T A = +25C 10 F CH = 8 MHz 9 8 7 6 5 4 3 2 1 0 4 2 3
Dividing -by-4
Dividing -by-4 Dividing -by-8 Dividing -by-16 Dividing -by-64
Dividing -by-8 Dividing -by-16 Dividing -by-64
5
6 V CC (V)
Characteristics of Current Consumption in the Main Sleep Mode I CCS vs. V CC I CCS (mA) 10 T A = +25C 9 F CH = 8 MHz 8 7 6 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 6 Dividing -by-4
Characteristics of Current Consumption in the Subclock Operation I CCSB vs. V CC I CCSB (A) 10 9 T A = +25C 8 F CL = 32.768 KHz 7 6 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 6
V CC (V) Characteristics of Current Consumption in the Subclock Stop I CCH vs. V CC I CCH (A) 2.0 1.8 T A = +25C F CL = 32.768 KHz 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2 2.5 3 3.5 4 4.5 5 5.5 6 V CC (V) 0 2 2.5 3 3.5 4 4.5 5 10 5 15
V CC (V) Characteristics of Current Consumption in the Watch Mode I CCT vs. V CC I CCT (A) 30 T A = +25C 25 F CL = 32.768 KHz 20
5.5 6 V CC (V)
40
MB89890 Series
(6) Pull-up Resistance
R PULL vs. VCC R PULL (k) 1000 T A = +25C 300
100 50
10 0 1 2 3 4 5 6 7 V CC (V)
41
MB89890 Series
s INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups: * * * * Transfer Arithmetic operation Branch Others
Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri x (x) (( x )) 42 Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Instruction Symbols Meaning
MB89890 Series
Columns indicate the following: Mnemonic: ~: #: Operation: TL, TH, AH: Assembler notation of an instruction The number of instructions The number of bytes Operation of an instruction A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH prior to the instruction executed. * 00 becomes 00. N, Z, V, C: OP code: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F.
43
MB89890 Series
Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP ,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) TL - - - - - AL AL AL AL AL AL AL - - - - - - - - - AL AL AL AL AL AL - - - - - - - - - - - - - - - AL AL - - - - TH - - - - - - - - - - - - - - - - - - - - - AH AH AH AH AH AH - - - - - - - - - - - - - - - - AH - - - - AH - - - - - - - - - - - - - - - - - - - - - dH dH dH dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH NZVC ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0
Notes: * During byte transfer to A, T A is restricted to low bytes. * Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)
44
MB89890 Series
Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) CA C A (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) TL - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - - - - - - - - - - - - - AH - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - - - - - - - - - - - - - - - - - - NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ ++-+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65
(Continued)
45
MB89890 Series
(Continued)
Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 # 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 # 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 TL - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - - NZVC ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ---- OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1
Branch Instructions (17 instructions) Operation TL - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - dH - - NZVC ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30
If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt Table 5
Other Instructions (9 instructions) Operation TL - - - - - - - - - TH - - - - - - - - - AH - dH - - - - - - - NZVC ---- ---- ---- ---- ---- ---R ---S ---- ---- OP code 40 50 41 51 00 81 91 80 90
Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI
~ 4 4 4 4 1 1 1 1 1
# 1 1 1 1 1 1 1 1 1
46
47
3 RETI SETC
PUSHW POPW MOV MOVW CLRI A A A,ext A,PS
L SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP ,A A,SP
H 4 5 6 7 8 9 A B C D E F
0
1
2
0
NOP
SWAP
RET
1 SUBC A A
MULU
DIVU
A XCH XOR AND OR A, T A A
A
PUSHW POPW MOV JMP CALL MOVW CLRC IX addr16 addr16 IX ext,A PS,A
2
ROLC
CMP
ADDC
A
A
A
MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX
s INSTRUCTION MAP
3 XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS
RORC
A
MOVW MOVW CLRB BBC INCW DECW MOVW MOVW CMPW ADDCW SUBCW XCHW XORW ANDW ORW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP ,A A,EP A CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC
MB89890 Series
4
MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8
5
SUBC A,@IX +d
@IX +d,#d8 @IX +d,#d8
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP ,#d16 A,SP
MOV @IX +d,A XOR AND A,@IX +d A,@IX +d OR A,@IX +d
6
MOV A,@IX +d
CMP A,@IX +d
ADDC A,@IX +d
MOV
CMP
CLRB BBC dir: 6 dir: 6,rel
MOVW MOVW A,@IX +d @IX +d,A
MOVW XCHW IX,#d16 A,IX
7
MOV CMP MOV CMP ADDC SUBC MOV XOR AND OR CLRB BBC MOVW MOVW MOVW XCHW ,#d8 @EP ,#d8 A,@EP A,@EP A,@EP A,@EP @EP ,A A,@EP A,@EP A,@EP @EP dir: 7 dir: 7,rel A,@EP @EP EP ,A ,#d16 A,EP
8
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel R0 R0 #0 rel rel rel rel
9
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel R1 R1 #1
A
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BP A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel R2 R2 #2
B
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BN A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel R3 R3 #3
C
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNZ A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel R4 R4 #4 rel rel
D
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BZ A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel R5 R5 #5
E
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BGE A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel R6 R6 #6 rel
F
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BLT A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel R7 R7 #7 rel
MB89890 Series
s MASK OPTIONS
Part number No. Specifying procedure Pull-up resistors * P00 to P07 * P10 to P17 * P30 to P37 * P40 to P44 * P60 to P67 * P70 to P77 * P80 to P87 * P90 to P97 * PA0 to PA7 MB89898/9
Specify when ordering masking
MB89P899
Specify with EPROM programmer
MB89PV890 Specifying not possible
1
Select by single pin * P00 to P07 * P10 to P17 * P30 to P37 * P40 to P44 * P60 to P67 * P70 to P77 * P80 to P87 * P90 to P97 * PA0 to PA7 Set in the above combinations
Select by 2-pin pair * P00 to P07 * P10 to P17 * P30 to P37 * P60 to P67 * P90 to P97 * PA0 to PA7 Select by single pin * P40 to P44 * P70 to P77 * P80 to P87 Set in the above combinations Selectable
Fixed to no pull-up resistor
2
Power-on reset (POR) * Power-on reset provided * No power-on reset Selection of the oscillation stabilization time (OSC) The oscillation stabilization time initial value can be set with WTM1 bit and WTM0 bit. Reset pin output (RST) * Reset output provided * No reset output Selection of clock mode (CLK) * Double clock mode * Single clock mode
Selectable Selectable WTM1 WTM0 0 0: 0 1: 1 0: 1 1: Selectable
Fixed to power-on reset optional
3
Selectable WTM1 WTM0 23/FCH 0 0: 12/FCH 2 0 1: 216/FCH 1 0: 218/FCH 1 1: Selectable
23/FCH 212/FCH 216/FCH 218/FCH
Fixed to oscillator stabilization 218/FCH
4
Fixed to reset output optional Fixed to double clock mode
5
Selectable
Selectable
s ORDERING INFORMATION
Part number MB89898PF MB89899PF MB89P899PF MB89PV890CF Package 100-pin Plastic QFP (FPT-100P-M06) 100-pin Ceramic MQFP (MQP-100C-P01) Remarks
48
MB89890 Series
s PACKAGE DIMENSION
100-pin Plastic QFP (FPT-100P-M06)
23.900.40(.941.016) 20.000.20(.787.008)
80 81 51 50
3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
100 31
17.900.40 (.705.016)
12.35(.486) REF
16.300.40 (.642.016)
"A" LEAD No.
1 30
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX Details of "B" part
0
10
0.800.20 (.031.008)
C
1994 FUJITSU LIMITED F100008-3C-2
Dimensions in mm (inches)
49
MB89890 Series
100-pin Ceramic MQFP (MQP-100C-P01)
17.200.40 SQ (.677.016) +0.30 12.00 -0.10 SQ
36
.472 -.004
+.012
25
2.70(.106)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
37
24
Details of "A" part 0.15(.006) 8.80 (.346) REF
13.600.40 (.535.016)
0.20(.008) 0.15(.006)MAX 0.50(.020)MAX
INDEX
48
"A"
13
Details of "B" part
LEAD No.
1
12
0.15 -0.01 0.300.06 (.012.002) "B" 0.16(.006)
M
+0.05 +.002
0.80(.0315)TYP
.006 -.0004 1.800.30 (.071.012)
0~10
0.15(.006)
C
1994 FUJITSU LIMITED F48026S-1C-1
Dimensions in mm (inches)
50
MB89890 Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9711 (c) FUJITSU LIMITED Printed in Japan
51

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